The present application is based on Japanese priority application No.11-193120 filed on Jul. 7, 1999, the entire contents of which are hereby incorporated by reference.
The present invention generally relates to memory controllers and information processing apparatuses having a memory controller. More particularly, the present invention is related to a memory controller controlling reading or writing operation of a memory device of a multiple-byte memory data width.
Recently, there is an intensive activity in developing a system LSI that includes a DRAM on a common semiconductor chip. Such a system LSI includes those carrying a RISC (Reduced Instruction Set Computer) processor or those carrying a processor devoted for graphic processing. By forming a DRAM integrally with a system LSI (Large Scale Integration), it is possible to reduce the size and power consumption of the electronic apparatus that uses the system LSI. Further, it becomes possible to increase the operational speed of the electronic apparatus.
In a system LSI, data read out from a memory such as DRAM is stored temporarily in a buffer unit, and a logic operation is carried out by a logic processing unit in the CPU (Central Processing Unit). Thereby, the data is stored in the memory unit with a predetermined byte width, and thus, reading of data is conducted based on the byte-width basis. By increasing the byte-width, it becomes possible to increase the data transfer rate without changing the access latency. Thus, there is a trend of technology to increase the byte width of a data bus.
FIG. 1 shows the data structure of a memory controller of a related art that includes a DRAM 10 and a buffer unit 12, wherein FIG. 1 shows reading out of data of 256 byte width. In the example of FIG. 1, it can be seen that the DRAM 10 has an n-byte memory data width (nxe2x89xa72) and the starting point of data reading is located on the boundary of the n-byte memory data width (hereinafter called as xe2x80x9cword boundaryxe2x80x9d). In such a case, the 256 byte data is read out straightforward and transferred to the buffer unit 12. In such a case, the 256 byte capacity of the buffer unit 12 is just enough for holding the data read out from the DRAM 10.
However, the situation of FIG. 1 is not a general situation and the starting point of data reading is not always located on the word boundary. Often, the starting point of data reading is located at an intermediate location of the n-byte memory data width.
FIG. 2 shows the reading of 256 byte data from the DRAM 10 for the case in which the starting point is located at an intermediate location of the nbyte memory data width. As the reading of the data is conducted every n-byte width, the data block of the nbyte size including the starting point inevitably includes unnecessary data part before the starting point. Similarly, the data block of the n-byte size including the final point of reading includes unnecessary data part after the final point. Thus, it has been necessary to provide a capacity of at least 256+n bytes for the buffer unit 12 for holding the nbyte data block read out from the DRAM 10. Alternatively, it has been necessary to provide a data-packing unit between the DRAM 10 and the buffer unit 12 so as to extract the 256 byte data from the data of 256+n bytes read out from the DRAM 10 and supply the same to the buffer unit 12. However, such a construction has been complex and caused increase of cost of the memory controller.
Accordingly, it is a general object of the present invention to provide a memory controller wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a memory controller that can achieve reading or writing of data from or to a memory device with a simplified construction and improved efficiency.
Another object of the present invention is to provide a memory controller, including:
a memory unit having an n-byte memory data width:
a register unit consecutively reading out, in response to an enable signal supplied thereto, data from said memory unit with every n-byte size, said register unit further recording therein said data read out from said memory unit in the form of continuous data of 2nxe2x88x921 bytes including the last data read out from said memory unit;
a shifter unit selecting consecutively, in response to a shift signal supplied thereto, a block of continuous n-byte data from said continuous data of 2nxe2x88x921 bytes recorded in said register unit, said shifter unit supplying said continuous n-byte data block to an output terminal; and
a control unit controlling said memory unit, said register unit and said shifter unit.
According to the present invention, requested data is selectively and efficiently read out from the memory unit according to the data width of the memory unit, even in such a case in which the starting point of data reading is located at an intermediate location of the memory data width.
Another object of the present invention is to provide a memory controller, including:
a memory unit having an n-byte memory data width;
a register unit consecutively receiving, in response to an enable signal supplied thereto, data from an external unit having n-byte size, said register unit further recording therein said data in the form of continuous data of 2n-1 bytes including the last received data;
a shifter unit selecting consecutively, in response to a shift signal supplied thereto, a continuous n-byte data block from the continuous data of 2nxe2x88x921 bytes recorded in said register unit, said shifter unit storing said continuous n-byte data block in a specified location of said memory unit; and
a control unit controlling said memory unit, said register unit and said shifter unit.
According to the present invention, efficient writing of data into the memory unit becomes possible even in such a case in which the starting point of data writing is located at an intermediate position of the memory data width.
Another object of the present invention is to provide a memory controller, including:
a memory unit having a n-byte memory data width;
a register unit carrying out, in response to an enable signal supplied thereto, one of a reading operation reading out data consecutively from said memory unit with every n-byte size and a receiving operation receiving data consecutively from an external unit with every n-byte size, said register unit further recording therein said data read out from said memory unit or received from said external unit in the form of continuous data of 2nxe2x88x921 bytes including the last acquired data;
a shifter unit selecting consecutively, in response to a shift signal supplied thereto, a block of continuous n-byte data from said continuous data of 2nxe2x88x921 bytes recorded in said register unit, said shifter unit supplying said continuous n-byte data block to an output terminal when in a mode of said reading operation, said shifter unit storing said continuous n-byte date block in a specified location of said memory unit when in a mode of said receiving operation; and
a control unit controlling said memory unit, said register unit and said shifter unit.
According to the present invention, it becomes possible, when the memory controller is in the reading operation mode, to read out only those required data from the memory unit, even in such a case in which the starting point of data reading is located at an intermediate location of the memory data width. When in the receiving operation mode, on the other hand, the memory controller writes only those required data into the memory unit even in such a case in which the starting point of data writing is located at an intermediate location of the memory data width.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.